1. Field of the Invention
The present invention relates to a fabrication method for a chip size package (CSP) type package which has an LSI (Large Scale Integrated Circuit) mounted therein.
2. Description of the Related Art
Conventional semiconductor CSP type packages for are classified into a build-up type CSP type package and a CSP type package fabricated by the wafer level CSP technology. FIG. 1 is an exemplary cross-sectional view of a conventional build-up type semiconductor CSP type package 110. In the build-up type CSP type package 110, a plurality of CSP pads 103 are formed on the top surface of a substrate 107 made of an organic material, such as glass epoxy or polyimide, and a plurality of external pads 105 are formed on the bottom surface of the substrate 107. The CSP pads 103 are electrically connected to the external pads 105 by CSP internal wires 104 formed inside the substrate 107. Formed respectively on the respective CSP pads 103 are CSP balls 102 on which an LSI chip 101 is mounted. Solder balls 106 are formed on the respective external pads 105 formed on the bottom surface of the substrate 107. The LSI chip 101 is electrically connected to the CSP internal wires 104, formed inside the substrate 107, via the CSP balls 102 and the CSP pads 103. The CSP internal wires 104 are electrically connected to an external board (not shown), such as a printed circuit board, via the external pads 105 and the solder balls 106.
FIG. 2A to FIG. 5B illustrate a fabrication method for the build-up type semiconductor CSP type package 110 according to the prior art. In the fabrication method for the conventional build-up type semiconductor CSP type package, as shown in FIG. 2A, first a plurality of via holes 107b penetrating through a substrate core member 107a, made of an organic material, such as glass epoxy or polyimide, are bored at desired positions on the substrate core member 107a. Next, a metal film of aluminum, copper or the like is deposited on the entire surface of the substrate core member 107a having the via holes 107b bored therein by a known plating technology, and at the same time, the via holes 107b are buried with the same metal. Then, wires are patterned by known photolithography and etching technologies, thereby forming a wiring pattern 104 as shown in FIG. 2B. Then, a lamination plate 107d made of an organic material, such as glass epoxy or polyimide, is adhered to both sides of the substrate core member 107a with the wiring pattern 104, and a plurality of via holes 107c are formed in those lamination plates 107d, as shown in FIG. 2C. Next, in the manner mentioned above, the via holes 107c formed in the lamination plates 107d are buried with the metal by the known plating technology and the wiring pattern 104 is formed on those surfaces of the lamination plates 107d which are not adhered to the substrate core member 107a by the photolithography technology and the etching technology. As shown in FIG. 124D, the process of burying the via holes 107c with the metal to form the wiring pattern 104 forms the CSP pads 103 and the external pads 105 on the surfaces of the lamination plates 107d simultaneously. Then, a protection film 107e is formed on the entire surface of each lamination plate 107d by a known coating scheme. Finally, the process that combines the photolithography technology and etching technology or the like removes the protection films 107e formed on the CSP pads 103 and the external pads 105 and provides openings through which the CSP pads 103 and external pads 105 are electrically connected to the outside.
The substrate 107 fabricated in the above manner is electrically connected to the LSI chip 101 via the CSP balls 102 as shown in FIG. 3, and is electrically connected to an external board (not shown), such as a printed circuit board, via the solder balls 106. In the process of mounting the LSI chip 101 on the substrate 107 and assembling the build-up type semiconductor CSP type package 110, first, the CSP balls 102 are arranged on LSI pad electrodes (not shown) formed on the surface of the LSI chip 101. After alignment is carried out in such a way that the CSP balls 102 are aligned with the CSP pads 103 formed on the substrate 107, the LSI chip 101 is mounted on the substrate 107. Eutectic solder, leadless solder or the like is used for the CSP balls 102. Solder bumps or gold bumps may be used instead of the CSP balls 102. At the time of mounting the LSI chip 101 on the substrate 107, for example, a metal flux or the like is coated on the surfaces of the CSP pads 103 after which the CSP balls 102 on the LSI chip 101 are pressure-bonded to the CSP pads 103 on the substrate 107 to be physically and electrically connected together while being heated at a temperature of around about 210° C. in case of using eutectic solder for the CSP balls 102 or at a temperature of around about 260° C. in case of using leadless solder for the CSP balls 102. In case where gold bumps are used instead of the CSP balls 102, the heating temperature is often set to around about 300° C. Next, the solder balls 106 are adhered onto the external pads 105 on the substrate 107 having the LSI chip 101 mounted thereon by using a method similar to the method of connecting the CSP balls 102 to the CSP pads 103. Bumps may be used in place of the solder balls 106. The solder balls 106 may be attached to the substrate 107 after fabrication of the substrate 107 but before mounting of the LSI chip 101 on the substrate 107.
The fabrication process for the substrate 107 is carried out with a plurality of substrates 107 linked to one another by a frame 111 as shown in FIG. 4A. Then, after those substrates 107 are cut out of the frame 111, the LSI chip 101 is mounted on each separated substrate 107 to assemble the build-up type CSP type package 110, as shown in FIG. 4B. In another available method, after multiple CSP type packages 110 are fabricated as a single CSP aggregation 112 as shown in FIG. 5A, LSI chips 101 are mounted on the LSI-chip mount portions of the respective CSP type packages 110, then the respective CSP type packages 110 with the LSI chips 101 mounted thereon are cut out as shown in FIG. 5B.
Such build-up type semiconductor CSP type packages are actually used to meet the demands of miniaturization of packages and higher package density that have been made with the recent improvements on the scale of LSIs. In various kinds of semiconductor packaging, the multi-pin layout and multilayering that have been taken to cope with an increase in the number of wires are advancing rapidly. In the build-up type CSP type packages, the multi-pin layout and multilayering, designed to cope with an increase in the number of wires, are coped with, for example, a scheme of laminating substrates made of an organic base material, such as glass epoxy or polyimide. In the conventional build-up type CSP type packages, however, the lamination of substrates made of an organic base material, such as glass epoxy or polyimide, to achieve the multi-pin layout and multilayering brings about a problem of making such a package heavy. Further, the multi-pin layout and multilayering on the package level increase the number of steps required in the fabrication and make the fabrication time longer. This leads to an increase in the manufacturing cost including the development cost and increases the unit price of fabricated packages.
In the wafer level CSP technology according to another prior art, a package fabricating process and the LSI chip assembling process are integrated. This prior art therefore reduces the packaging cost significantly and can fabricate a semiconductor CSP type package with an LSI chip mounted therein at a high density with a size equal to or slightly larger than the size of the LSI chip. The wafer level CSP technology can therefore fabricate smaller semiconductor CSP type packages at a higher density at a lower cost as compared with the technology of fabricating build-up type CSP type packages.
FIG. 6 to FIG. 11B illustrate a fabrication process for a semiconductor CSP type package according to the invention the conventional wafer level CSP technology. FIG. 6 is a cross-sectional view of a semiconductor CSP type package 61 according to the conventional wafer level CSP technology. In the semiconductor CSP type package 61, as shown in FIG. 6, LSI pads 52 are formed on an LSI chip 51 as electrodes to obtain electrical connection from the LSI chip 51. The entire surface of the LSI chip 51, excluding those portions where the LSI pads 52 are formed, is covered with a first resin coat layer 53. First contact electrodes 54 are formed on the LSI pads 52 to obtain electrical connection from the LSI chip 51 via the LSI pads 52. An intermediate wire layer 55 which routes out wires to transmit electrical signals into the semiconductor CSP type package 61 is formed on parts of the first resin coat layer 53 including those lying above the first contact electrodes 54. Second contact electrodes 57 are formed on parts of the intermediate wire layer 55, and an insulative second resin coat layer 56 buries an area around each second contact electrode 57, excluding that portion lying above the second contact electrode 57, to electrically isolate the second contact electrodes 57 from one another. CSP pads 58 are formed on those portions of the second contact electrodes 57 which are not covered with the second resin coat layer 56 as electrodes to transmit electrical signals from the LSI chip 51 to an external board or the like (not shown). CSP bumps 59 which become external output terminals of the semiconductor CSP type package 61 are formed in such a way as to cover the CSP pads 58. The semiconductor CSP type package 61 according to the wafer level CSP technology is connected to connection terminals of an external wire substrate or the like (not shown), such as a printed circuit board, via the CSP bumps 59.
In the conventional semiconductor CSP type package 61 according to the wafer level CSP technology, as electrical signals output from the LSI chip 51 pass the LSI pads 52, the first contact electrodes 54, the intermediate wire layer 55, the second contact electrodes 57, the CSP pads 58 and the CSP bumps 59 in order, the electrical signals are transmitted to a wire board or the like, such as a printed circuit board, outside the semiconductor CSP type package 61. As electrical signals from a wire board or the like, such as a printed circuit board, outside the semiconductor CSP type package 61 pass in the route in the reverse order, the electrical signals are transmitted to the LSI chip 51h. The CSP bumps 59 are arranged at arbitrary positions inside LSI chip side lines 60 which are the periphery of the semiconductor CSP type package 61 as the intermediate wire layer 55 is routed around within the semiconductor CSP type package 61. Although FIG. 6 shows an example where only a single intermediate wire layer 55 is provided, there is no restriction on the number of intermediate wire layers 55 and a plurality of intermediate wire layers 55 technically allowable can be formed.
FIG. 7 is a plan view of the semiconductor CSP type package 61 according to the conventional wafer level CSP technology. The LSI chip 51 and the semiconductor CSP type package 61 are almost equal in size. The positions of the LSI pads 52 do not necessarily coincide with the positions of the CSP bumps 59 but are arranged extremely close thereto.
A description will now be given of the method of fabricating a semiconductor CSP type package according to the wafer level CSP technology. FIG. 8A shows a wafer 71 which has undergone the diffusion process or the final process of the wafer process (preprocess of semiconductor fabrication). Scribe lines 72 or the boundary lines of the individual LSI chips 51 run vertically and horizontally on the surface of the wafer 71 whose wafer process has been completed. FIG. 8B shows the cross section of the wafer 71. Formed on each LSI chip 51 formed on the surface of the wafer 71 by the wafer process are the LSI pads 52 that connect the LSI chip 51 to the semiconductor CSP type package 61 on which the LSI chip 51 is mounted. The LSI pads 52 are formed by depositing a metal, such as aluminum, on the entire surface of the wafer 71 by known CVD (Chemical Vapor Deposition), then patterning a pad pattern by known photolithography and etching technologies. The entire surface of the wafer 71, excluding those portions lying above the LSI pads 52, is covered with an insulative film (not shown) of silicon oxide, silicon nitride, polyimide or the like. This can allow the wafer 71 to keep the electrical insulation and protect the wafer 71 against mechanical and chemical impacts.
According to the conventional wafer level CSP technology, as shown in FIGS. 9A to 9C, first, the first resin coat layer 53 is formed in such a way as to cover the entire surface of the wafer 71. FIG. 9A is a plan view illustrating the fabrication method for the semiconductor CSP type package according to the conventional wafer level CSP technology, FIG. 9B is a cross-sectional view of the semiconductor CSP type package, and FIG. 9C is a partly enlarged view of the semiconductor CSP type package in FIG. 9B. One way of forming the first resin coat layer 53 is to coat a thermosetting polyimide having a high thermal fluidity on the wafer 71 by a known spin coating scheme or the like and then heating the wafer 71 to a temperature of 100° C. to 150° C. to cure the coated film of polyimide, thereby providing a resin coat layer. Another method is to adhere a thin resin sealing film 53a onto the wafer 71. In the method of adhering the thin resin sealing film 53a on the wafer 71, the wafer 71 adhered with the thin resin sealing film 53a is held by a hot plate or the like and heated to about 100° C. to pressure-bonding the thin resin sealing film 53a onto the entire surface of the wafer 71, thereby forming the first resin coat layer 53.
Next, a photoresist is applied onto the wafer 71 with the first resin coat layer 53 formed thereon and the photoresist applied onto the first resin coat layer 53 that is formed on the LSI pads 52 on the wafer 71 is removed by the known photolithography technology. Then, the first resin coat layer 53 on the LSI pads 52 is removed by the known etching technology or laser processing technology or the like to thereby form contact holes 81 in the LSI pads 52 as shown in FIG. 10A.
Next, a metal film of as aluminum, copper or the like is formed on the entire surface of the wafer 71 having the contact holes 81 formed therein by using the known plating technology. Accordingly, the contact holes 81 are buried with the metal, such as aluminum or copper. The metal that is deposited on the other portion of the surface of the wafer 71 than the contact holes 81 is removed by a known etch-back technology or the like. As the contact holes 81 are buried with the metal, such as aluminum or copper, this way, the first contact electrodes 54 are formed. In addition to the contact electrode forming method that employs the combination of the etching technology and the plating technology, there is another known method which forms the first resin coat layer 53 and the first contact electrodes 54 by forming columnar posts of metal such as copper before forming the first resin coat layer 53 and then covering the posts with an insulative resin using a known mold sealing technique.
Next, metal, such as copper or gold, is deposited on the entire surface of the wafer 71 with the first contact electrodes 54 formed thereon by the known plating technology and the intermediate wire layer 55 is formed on the first resin coat layer 53 including those portions above the first contact electrodes 54 as shown in FIG. 132B by the known photolithography and etching technologies.
Then, the second resin coat layer 56 is formed in the same method as used in forming the first resin coat layer 53, and the second contact electrodes 57 and the CSP pads 58 are formed in the same method as used in forming the first contact electrodes 54. Metal, such as aluminum or copper, is pressure-bonded onto the CSP pads 58 while being heated using a dispenser, thus forming the CSP bumps 59 as shown in FIG. 11A. Instead of the CSP bumps 59, solder balls may be used.
Finally, the wafer 71 with the CSP bumps 59 formed thereon is cut away along the scribe lines 72 by a diamond cutter, a laser or the like, yielding individual semiconductor CSP type packages 61.
The conventional semiconductor CSP type packages according to the wafer level CSP technology, which are fabricated in the above-described manner, do not raise the problem of the build-up type CSP type packages such that the weight is significantly increased due to the multi-pin layout and multilayering on the package level.
With the recent larger scale integration of LSIs, however, the pitches of the external terminals or the connection portions to an external board, such as a printed circuit board, tends to become extremely narrower in the conventional semiconductor CSP type packages according to the wafer level CSP technology. A socket is used in a test of checking the functional operation of an LSI (hereinafter referred to as “screening process”) after the LSI chip is mounted in the package. If the socket that corresponds to the very narrow pitches of the external terminals is selected, it becomes very expensive. In the semiconductor CSP type package according to the wafer level CSP technology, the pitches of the external terminals are about 400 μm or less and the intervals between the terminals are generally about 100 μm. This restricts the number of wires that run between terminals on an external board, such as a printed circuit board. Therefore, an external board, such as a printed circuit board, should face with the increasing necessity of achieving multilayering of wire layers, thus raising the problems of a cost increase, the extension of the fabrication period and so forth. While the semiconductor CSP type package according to the wafer level CSP technology suffer the prominent problem originated from the extremely narrow pitches of the contact terminals to an external board, the conventional wafer level CSP technology suffers a limitation to the area where the external terminals can be provided due to the package size being determined by the size of the LSI chip to be mounted. Therefore, widening the pitches of the external terminals reduces the number of the providable external terminals, thus limiting the degree of freedom on the interconnection design.
Japanese Patent Laid-Open No. 2001-15650 points out the problem of short-circuiting of interconnections that would originate from melting of solder bumps on the external terminals adjoining to one another at the extremely narrow pitches at the time of connecting the external terminals to an external board, such as a printed circuit board, and discloses the technique of mounting a semiconductor CSP type package on an external board by connecting the external terminals to the wire conductors without soldering but by metal plating.
Of many problems that would arise due to the very narrow pitches of the external terminals, however, only the problem of wire short-circuiting that would occur on the external terminals is overcome by the prior art, but the other problems are not overcome. In other words, the prior art fails to teach or suggest the ways of facilitating the wire layout design on an external board and avoiding the multilayering of wires on the external board, thereby suppressing an increase in fabrication cost and shortening the fabrication period. Therefore, the prior art does not disclose any specific means of solving the problem that would occur from the package size being determined by the size of the LSI chip to be mounted.